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rev. pra information furnished by analog devices is believed to be accurate and reliable. however, no responsibility is assumed by analog devices for its use, nor for any infringements of patents or other rights of third parties which may result from its use. no license is granted by implication or otherwise under any patent or patent rights of analog devices. a AD9803 one technology way, p.o. box 9106, norwood, ma 02062-9106, u.s.a. tel: 781/329-4700 world wide web site: http://www.analog.com fax: 781/326-8703 ? analog devices, inc., 1998 preliminary technical data preliminary technical data ccd signal processor for electronic cameras functional block diagram pga 0C30db 0C10db pga clamp 3 ref 10b dac 8b dac 8b dac intf AD9803 10 pblk pgacont1-2 clpob 3-w intf adcin auxin aclp shp shd adcclk dout auxcont vrt vrb ccdin dac1 dac2 clpdm timing generator mux s/h clamp cds clamp adc features 3-wire serial i/f for digital control 21 mhz correlated double sampler low noise pga with 0 dbC30 db range analog pre-blanking function aux input with input clamp and pga 10-bit 27 msps a/d converter direct adc input with input clamp internal voltage reference two auxiliary 8-bit dacs +3 v single supply operation low power cmos: 190 mw 48-lead lqfp package product description the AD9803 is a complete ccd and video signal processor developed for electronic cameras. it is well suited for video camera and still-camera applications. the 21 mhz ccd signal processing chain consists of a cds, low noise pga, and 10-bit adc. required clamping circuitry and a v oltage reference are also provided. the aux input features a wideband pga and input clamp, and operates up to 27 mhz. the AD9803 operates from a 3 v supply with a power con- sumption of 190 mw. the AD9803 is packaged in a space saving 48-lead lqfp and is specified over an operating tem- perature range of C20 c to +75 c.
C2C rev. pra AD9803Cspecifications preliminary technical data general specifications parameter min typ max units temperature range operating C20 70 c storage C65 150 c power supply voltage analog 2.7 3.3 3.6 v digital 2.7 3.3 3.6 v digital driver 2.7 3.3 3.6 v power consumption (power-down modes selected through serial i/f) normal operation (d-reg 00) (specified under each mode of operation) standby mode (d-reg 01) 30 mw reference standby (d-reg 10 or stby pin hi) 10 mw shutdown mode (d-reg 11) 10 mw maximum clock rate (specified under each mode of operation) s/h amplifier gain 0db clock rate 27 mhz a/d converter resolution 10 bits differential nonlinearity 0C255 code 0.5 0.8 lsbs 256C1023 code 0.5 1.0 lsbs no missing codes guaranteed full-scale input range 1.0 v p-p clock rate 27 mhz reference reference top voltage 1.75 v reference bottom voltage 1.25 v specifications subject to change without notice. digital specifications parameter symbol min typ max units logic inputs high level input voltage v ih 2.1 v low level input voltage v il 0.6 v high level input current i ih 10 m a low level input current i il 10 m a input capacitance c in 10 pf logic outputs high level output voltage v oh 2.1 v low level output voltage v ol 0.6 v high level output current i oh 50 m a low level output current i ol 50 m a specifications subject to change without notice.
C3C rev. pra AD9803 preliminary technical data ccd-mode specifications parameter min typ max units power consumption 190 mw maximum clock rate 21 mhz cds gain 0db allowable ccd reset transient 1 500 mv max input range before saturation 1 1000 mv p-p pga max input range 1000 mv p-p max output range 1000 mv p-p digital gain control gain control resolution 10 (fixed) bits gain (selected through serial i/f) gain(0) gain(100) 0 db gain(1023) gain(820) 30 db analog gain control pgacont1 = 0.3 v, pgacont2 = 1.5 v 0 db pgacont1 = 2.4 v, pgacont2 = 1.5 v 30 db pgacont1 gain slope 14.3 db/v pgacont2 gain slope 0.89 db/v black-level clamp clamp level (selected by the serial i/f) clp(0) (e-reg 00) 32 lsb clp(1) (e-reg 01) 48 lsb clp(2) (e-reg 10) 64 lsb clp(3) (e-reg 11) 16 lsb timing specifications 3 pipeline delay even-odd offset correction disabled 5 cycles even-odd offset correction enabled 7 cycles internal clock delay 4 (t id )3 ns inhibited clock period (t inihibit )15 ns output delay (t od ) 20 ns output hold time (t hold )2 ns adcclk, shp, shd, clock period 47 n s adcclk hi-level, or low-level 20 n s shp, shd minimum pulsewidth 5 10 ns shp rising edge to shd rising edge 20 ns notes 1 input range is defined as the peak-to-peak difference between the ccd's reference and data levels 3 20 pf loading; timing shown in figure 1. 4 internal aperture delay for actual sampling edge. specifications subject to change without notice.
C4C rev. pra AD9803Cspecifications preliminary technical data aux-mode specifications parameter min typ max units power consumption 100 mw maximum clock rate 27 mhz pga max input range 700 mv p-p max output range 1000 mv p-p digital gain control gain control resolution 8 bits gain (selected by the serial i/f) gain(0) 0 db gain(255) 10 db analog gain control auxcont = 0.3 v 0 db auxcont = 2.4 v 10 db auxcont gain slope 4.167 db/v auxcont stable range 0.3 2.7 v active clamp (clamp on) clamp level (selectable by the serial i/f) clp(0) (e-reg 00) 32 lsb clp(1) (e-reg 01) 48 lsb clp(2) (e-reg 10) 64 lsb clp(3) (e-reg 11) 16 lsb timing specifications 1 pipeline delay 4 (fixed) cycles internal clock delay (t id ) 5ns output delay (t od ) 20 ns output hold time (t hold )2 ns notes 1 20 pf loading; timing shown in figure 2. specifications subject to change without notice. adc-mode specifications parameter min typ max units power consumption 100 mw maximum clock rate 27 mhz active clamp (same as aux-mode) timing specifications (same as aux-mode) specifications subject to change without notice. dac specifications (dac1 and dac2) parameter min typ max units resolution 8 (fixed) bits min output 0.15 v max output vddC0.15 v max current load 1 ma max capacitive load 500 pf specifications subject to change without notice.
AD9803 C5C rev. pra preliminary technical data timing specifications n n+1 n+2 n+3 n+4 t inhibit t id t id t od t h old adcclk rising edge placement nC7 nC6 nC5 nC4 nC3 nC2 ccd shp shd adcclk d0Cd9 notes: 1. shp and shd should be optimally aligned with the ccd signal. samples are taken at the rising edges. 2. adcclk rising edge must occur at least 15ns after the rising edge of shp ( t inhibit ). 3. recommended placement for adcclk rising edge is between the rising edge of shd and falling edge of shp. 4. output latency (7 cycles) shown with even-odd offset correction enabled. 5. active low clock pulse mode is shown. figure 1. ccd-mode timing t id t od t hold n n+1 n+2 n+3 n+4 nC4 nC3 nC2 n+5 video input adcclk d0Cd9 nC1 n note: example of output data latched by adcclk rising edge. figure 2. aux-mode and adc-mode timing ccd signal clpob clpdm pblk effective pixels optical black blanking interval dummy black effective pixels notes: 1. clpob pulsewidth should be a minimum of 10 ob pixels wide, 20 ob pixels are recommended. 2. clpdm pulsewidth should be at least 1 m s wide. 3. pblk is not required, but recommended if the ccd signal amplitude exceeds 1v p-p. 4. clpob and clpdm overwrite pblk. 5. active low clamp pulse mode is shown. figure 3. ccd-mode clamp timing figure 4. aux-mode clamp timing
AD9803 C6C rev. pra preliminary technical data absolute maximum ratings* parameter with respect to min max units advdd advss, subst C0.3 6.5 v acvdd acvss, subst C0.3 6.5 v dvdd dvss C0.3 6.5 v drvdd drvss C0.3 6.5 v clock inputs dvss C0.3 dvdd + 0.3 v pgacont1, pgacont2 subst C0.3 acvdd + 0.3 v pin, din subst C0.3 acvdd + 0.3 v dout drvss C0.3 drvdd + 0.3 v vrt, vrb subst C0.3 advdd + 0.3 v ccdbyp1, ccdbyp2 subst C0.3 acvdd + 0.3 v dac1, dac2 subst C0.3 advdd + 0.3 v drvss, dvss, acvss, advss subst C0.3 +0.3 v junction temperature +150 c storage temperature C65 +150 c lead temperature (10 sec) +300 c *stresses above those listed under absolute maximum ratings may cause permanent damage to the device. this is a stress rating o nly; functional operation of the device at these or other conditions above those indicated in the operational sections of this specification is not implied. exposure t o absolute maximum ratings for extended periods may affect device reliability. ordering guide model temperature range package description package option AD9803jst 0 c to +70 c 48-lead plastic thin quad flatpack st-48 caution esd (electrostatic discharge) sensitive device. electrostatic charges as high as 4000 v readily accumulate on the human body and test equipment and can discharge without detection. although the AD9803 features proprietary esd protection circuitry, permanent damage may occur on devices subjected to high energy electrostatic discharges. therefore, proper esd precautions are recommended to avoid performance degradation or loss of functionality. warning! esd sensitive device note: aclp can be used two different ways. to control the exact time of the clamp, an active low pulse is used to specify the clamp interval. alternatively, aclp may be tied to ground. in this configuration, the clamp circuitry will sense the most timing specifications (continued) h sync manual clamping automatic clamping video signal aclp negative portion of the signal and use this level to set the clamp voltage. for the video waveform in figure 4, the sync level will be clamped to the black level specified in the e-register. active low clamp pulse mode is shown.
AD9803 C7C rev. pra preliminary technical data pin function descriptions p in # pin name type description 1 nc no connect (should be left floating or tied to ground) 2C11 d0Cd9 do digital data outputs 12 drvdd p digital driver supply (3 v) 13 drvss p digital driver ground 14 dvss p digital ground 15 aclp p aux-mode/adc-mode clamp 16 adcclk di adc sample clock input 17 dvdd p digital supply (3 v) 18 stby di power-down mode (active hi/internal pull-down) 19 pblk di pixel blanking 20 clpob di black level restore clamp 21 shp di ccd reference sample clock input 22 shd di ccd data sample clock input 23 clpdm di input clamp 24 nc no connect (should be left floating or tied to ground) 25 ccdbyp2 ao cds ground bypass (0.1 m f to ground) 26 din ai cds negative input (tie to pin 27 and ac-couple to ccd input signal) 27 pin ai cds positive input (see above) 28 ccdbyp1 ao cds ground bypass (0.1 m f to ground) 29 pgacont1 ai pga coarse gain analog control 30 pgacont2 ai pga fine gain analog control 31 acvss p analog ground 32 clpbyp ao bias bypass (0.1 m f to ground) 33 acvdd p analog supply (3 v) 34 auxin ai aux-mode input 35 auxcont ai aux-mode pga gain analog control 36 adcin ai adc-mode input 37 cmlevel ao common-mode level (0.1 m f to ground) 38 vtrbyp ao bias bypass (0.1 m f to ground) 39 dac1 ao dac1 output 40 dac2 ao dac2 output 41 sl di serial i/f load signal 42 sck di serial i/f clock 43 advdd p analog supply (3 v) 44 sdata di serial i/f input data 45 advss p analog ground 46 subst p analog ground 47 vrb ao bottom reference (0.1 m f to ground and 1 m f to vrt) 48 vrt ao top reference (0.1 m f to ground) note type: ai = analog input, ao = analog output, di = digital input, do = digital output, p = power. pin configuration 36 35 34 33 32 31 30 29 28 27 26 25 13 14 15 16 17 18 19 20 21 22 23 24 1 2 3 4 5 6 7 8 9 10 11 12 48 47 46 45 44 39 38 37 43 42 41 40 pin 1 identifier top view (not to scale) dvdd dvss aclp adcclk stby nc (lsb) d0 d1 d2 d3 d4 d5 d6 d7 d8 (msb) d9 drvdd pblk clpob shp shd AD9803 nc adcin auxcont auxin acvdd clpbyp acvss pgacont2 pgacont1 ccdbyp1 pin din ccdbyp2 vrt vrb subst advss sdata advdd sck sl dac2 dac1 vtrbyp cmlevel clpdm drvss nc = no connect
AD9803 C8C rev. pra preliminary technical data modes2 sdata select dac2 dac1 pga modes a2 1 1 0 0 0 a1 1 0 1 1 0 a0 1 0 1 0 1 d9 d8 d7 d6 d5 d4 d3 d2 d1 d0 a1 a0 b1 b0 c1 c0 d1 d0 e1 e0 operation modes output modes clock modes power down modes clamp level f9 f8 f7 f6 f5 f4 f3 f2 f1 f0 pga gain level selection g7 g6 g5 g4 g3 g2 g1 g0 h7 h6 h5 h4 h3 h2 h1 h0 j0 k0 0 m0 dac1 input dac2 input operation and power down modes shift register f-reg f0Cf9 e-reg e0Ce1 d-reg (d) power down modes d0Cd1 c-reg c0Cc1 b-reg b0Cb1 a-reg (a) operation modes a0Ca1 (b) output modes (c) clock modes (e) clamp level (f) pga gain m-reg m0 k-reg (k) external pga gain control k0 j-reg j0 h-reg h0Ch7 g-reg (g) dac1 input g0Cg7 (h) dac2 input (j) even-odd offset correction (m) dac1 and dac2 power down select figure 33. internal register map
AD9803 C9C rev. pra preliminary technical data register description (a) a-register: modes of operation a1 a0 modes 0 0 adc-mode 0 1 aux-mode 1 0 ccd-mode 1 1 ccd-mode (b) b-register: output modes b 1 b 0 d9 d8 d7 d6 d5 d4 d3 d2 d1 d0 0 0 normal 0 1 0101010101 1 0 1010101010 1 1 high impedance (c) c-register: clock modes c1 c0 shp-shd clock pulses clamp active pulses 0 0 active low active low 0 1 active low active high 1 0 active high active low 1 1 active high active high (d) d-register: power-down modes modes d1 d0 description normal 0 0 normal operation power-down 1 0 1 stand-by mode (fast recovery) power-down 2 1 0 reference stand-by (same mode as stby pin 18) power-down 3 1 1 total shut-down (e) e-register: clamp level selection e1 e0 clamp level clp(0) 0 0 32 lsbs clp(1) 0 1 48 lsbs clp(2) 1 0 64 lsbs clp(3) 1 1 16 lsbs (f) f-register: pga gain selection f9 f8 f7 f6 f5 f4 f3 f2 f1 f0 ccd-gain gain(0) 0 0 0 0 0 0 0 0 0 0 0.00 db gain(1) 0 0 0 0 0 0 0 0 0 1 0.03 db ... ... gain(1022) 1 1 1 1 1 1 1 1 1 0 29.97 db gain(1023) 1 1 1 1 1 1 1 1 1 1 30.0 db (f) f-register: pga gain selection f9 f8 f7 f6 f5 f4 f3 f2 aux-gain gain(0) 0 0 0 0 0 0 0 0 0.00 db gain(1) 0 0 0 0 0 0 0 1 0.04 db ... ... gain(254) 1 1 1 1 1 1 1 0 9.96 db gain(255) 1 1 1 1 1 1 1 1 10.00 db (g) g-register: dac1 input g7 g6 g5 g4 g3 g2 g1 g0 dac1 output* code(0) 0 0 0 0 0 0 0 0 0 v code(1) 0 0 0 0 0 0 0 1 0.012 v ... ... code(254) 1 1 1 1 1 1 1 0 2.988 v code(255) 1 1 1 1 1 1 1 1 3.0 v (h) h-register: dac2 input h7 h6 h5 h4 h3 h2 h1 h0 dac2 output* code(0) 0 0 0 0 0 0 0 0 0 v code(1) 0 0 0 0 0 0 0 1 0.012 v ... ... code(254) 1 1 1 1 1 1 1 0 2.988 v code(255) 1 1 1 1 1 1 1 1 3.0 v (j) j-register: even-odd offset correction j0 even-odd offset correction 0 offset correction in use 1 offset correction not used (k) k-register: external pga gain control k0 pga gain control 0 external voltage control through auxcont or pgacont1 and pgacont2 1 internal 10-bit dac control of pga gain (m) m-register: dac1 & dac2 pdn m0 power down of 28-bit dacs 0 8-bit dacs powered-down 1 8-bit dacs operational *vdd = 3 v
AD9803 C10C rev. pra preliminary technical data rising edge triggered t dh t ls t lh register loaded on rising edge rnw a0 a1 a2 d0 d1 d2 d3 d4 d5 d6 d7 d8 d9 sdata sck sl t ds figure 34. serial write operation sdata rnw a0 a1 a2 d0 d1 d2 d3 d4 d5 d6 d7 d8 d9 xx xx dummy bits ignored sck sl figure 35. 16-bit serial write operation note : with the exception of a write to the pga register during aux-mode, all data writes must be 10 bits. during an aux- mode write to the pga register, only 8 bits of data are re- quired. if more than 14 sck rising edges are applied during a write operation, additional sck pulses will be ignored (see figure 35). all reads must be 10 bits to receive valid register contents. all registers default to 0s on power-up, except for the a-register, which defaults to 11. thus, on power-up, the AD9803 defaults to ccd mode. during the power-up phase, it is recom- mended that sl be high and sck be low to prevent acci- dental register write operations. sdata may be unknown. the rnw bit (read/not write) must be low for all write opera- tions to the serial interface, and high when reading back from the serial interface registers.
AD9803 C11C rev. pra preliminary technical data outline dimensions dimensions shown in inches and (mm). 48-lead plastic thin quad flatpack (tqfp) (st-48) 0.354 (9.00) bsc 0.276 (7.0) bsc 1 12 13 25 24 36 37 48 top view (pins down) 0.276 (7.0) bsc 0.354 (9.00) bsc 0.009 (0.225) 0.006 (0.17) 0.019 (0.5) bsc seating plane 0.063 (1.60) max 0 min 0 C 7 0.076 max no min 0.030 (0.75) 0.018 (0.45) 0.057 (1.45) 0.053 (1.35) 0.030 (0.75) 0.018 (0.45) 0.007 (0.18) 0.004 (0.09)

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